Micron Technology DRAM SDRAM-DDR2, Part #: MT40A2G4SA-062E:R TR | Dynamic random access memory | DEX Phillips and Pair Polarity • MDC/MDIO

and Pair Polarity • MDC/MDIO Management Interface for PHY Register Configuration • Interrupt Pin Option • Power-Down and Power-Saving Modes • Operating Voltages - Core (DVDDL

SKU : GEC:5328696

Xilinx FPGA Part #XCZU4CG-1SFVC784I

This output is given as an input to the OTS lock

Micron Technology DRAM SDRAM-DDR2, Part #: MT40A2G4SA-062E:R TR | Dynamic random access memory | DEX Phillips and Pair Polarity • MDC/MDIOMicron Technology DRAM SDRAM DDR4, Part #: MT40A2G4SA 062E: R TR features: VDD = VDDQ = 1. 2V + 60mv VPP = 2. 5V, 125mV, + 250mV On die, internal, adjustable VREFDQ generation 1. 2V pseudo open drain I O Refresh time of 8192 cycle at TC temperature range: 16 internal banks (x4, x8): 4 groups of 4 banks each 8n bit prefetch architecture Programmable data strobe preambles Data strobe preamble training Command Address latency (CAL) Multipurpose register